Passivated and Faceted for Fin Field Effect Transistor

ABSTRACT

A fin field effect transistor (FinFET), and a method of forming, is provided. The FinFET has a fin having one or more semiconductor layers epitaxially grown on a substrate. A first passivation layer is formed over the fins, and isolation regions are formed between the fins. An upper portion of the fins are reshaped and a second passivation layer is formed over the reshaped portion. Thereafter, a gate structure may be formed over the fins and source/drain regions may be formed.

This application is a continuation of U.S. patent application Ser. No. 15/620,499, entitled “Passivated and Faceted for Fin Field Effect Transistor” filed on Jun. 12, 2017, which is a continuation of U.S. patent application Ser. No. 15/018,245, entitled “Passivated and Faceted for Fin Field Effect Transistor” filed on Feb. 8, 2016, now U.S. Pat. No. 9,680,021 issued Jun. 13, 2017, which is a divisional of U.S. patent application Ser. No. 14/051,033, now U.S. Pat. No. 9,287,262, entitled “Passivated and Faceted for Fin Field Effect Transistor” filed on Oct. 10, 2013, now U.S. Pat. No. 9,287,262 issued Mar. 15, 2016, which applications are hereby incorporated herein by reference.

BACKGROUND

As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design issues have resulted in the development of three-dimensional designs, such as a fin field effect transistor (FinFET). A typical FinFET is fabricated with a thin vertical “fin” (or fin structure) extending from a substrate formed by, for example, etching away a portion of a silicon layer of the substrate. The channel of the FinFET is formed in this vertical fin. A gate is provided over (e.g., wrapping) the fin. Having a gate on both sides of the channel allows gate control of the channel from both sides. In addition, strained materials in source/drain (S/D) portions of the FinFET utilizing selectively grown silicon germanium (SiGe) may be used to enhance carrier mobility.

However, there are challenges to implementation of such features and processes in complementary metal-oxide-semiconductor (CMOS) fabrication. For example, interface traps between fins and shallow-trench-isolation (STI) oxide cause high leakage current of the FinFET, thereby degrading the device performance.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure is best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 is a flowchart illustrating a method of fabricating a FinFET according to various aspects of the present disclosure;

FIG. 2 shows a top view of a FinFET comprising a passivation structure according to various aspects of the present disclosure;

FIGS. 3-10 are cross-sectional views of a FinFET at various stages of fabrication according to various embodiments of the present disclosure;

FIGS. 11-18 are cross-sectional views of a FinFET at various stages of fabrication according to various other embodiments of the present disclosure; and

FIGS. 19-26 are cross-sectional views of a FinFET at various stages of fabrication according to various other embodiments of the present disclosure.

DESCRIPTION

It is understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Referring to FIG. 1, illustrated is a flowchart of a method 100 of fabricating a fin field effect transistor (FinFET) according to various aspects of the present disclosure. The method 100 begins with step 102 in which a substrate, such as a silicon substrate, is provided. The method 100 continues with step 104 in which one or more semiconductor layers are formed over the substrate. In an embodiment, such as that disclosed below with reference to FIGS. 3-10, the one or more semiconductor layers comprise a silicon germanium epitaxially grown over the substrate and a germanium layer epitaxially grown over the silicon germanium layer. In another embodiment, such as that disclosed below with reference to FIGS. 11-18, a silicon germanium layer (gradient or uniform) is formed over the substrate. In yet another embodiment, such as that disclosed below with reference to FIGS. 19-26, the one or more semiconductor layers comprise a plurality of silicon germanium layers having differing concentrations of germanium.

In step 106, a plurality of trenches is formed through the one or more semiconductor layers and into the substrate, wherein fins are created between adjacent trenches. A first passivation layer, such as an oxynitride layer, is formed over the fins in step 108, followed by isolation regions being formed by depositing a dielectric material in the trenches in step 110. Exposed portions of the fins are reshaped and a second passivation layer, such as an oxynitride layer, is formed over the reshaped fins in step 112. Thereafter, a gate structure is formed in step 114. The discussion that follows illustrates embodiments of FinFETs that can be fabricated according to the method 100 of FIG. 1.

FIG. 2 shows a top view of a fin field effect transistor (FinFET) 200 comprising a passivation structure 230 formed over a fin structure 220 according to various aspects of the present disclosure. FIGS. 3-26 are cross-sectional views of a FinFET 200 taken along the line a-a of FIG. 2 at various stages of fabrication according to various embodiment of the present disclosure. As employed in the present disclosure, the FinFET 200 refers to any fin-based, multi-gate transistor. Other transistor structures and analogous structures are within the contemplated scope of the disclosure. The FinFET 200 may be included in a microprocessor, memory cell, and/or other integrated circuit (IC).

It is noted that the method of FIG. 1 does not produce a completed FinFET 200. A completed FinFET 200 may be fabricated using complementary metal-oxide-semiconductor (CMOS) technology processing. Accordingly, it is understood that additional processes may be provided before, during, and after the method 100 of FIG. 1, and that other processes may only be briefly described herein. Also, FIGS. 1-26 are simplified for a better understanding of the concepts of the present disclosure. For example, although the figures illustrate the FinFET 200, it is understood the IC may comprise a number of other devices comprising resistors, capacitors, inductors, fuses, etc.

FIG. 2 illustrates a FinFET 200 fabricated using the steps in FIG. 1. For illustration, the FinFET 200 comprises a fin structure 220 (dashed line), a passivation structure 230 surrounding the fin structure 220 and a gate structure 240 traversing over a channel portion of the fin structure 220. For illustration, the FinFET 200 comprises two fins. In some embodiments, the FinFET 200 may comprise less than or greater than two fins, for example, one fin or three fins.

FIGS. 3-10 illustrate various cross-sectional views of intermediate steps of fabricating a FinFET device in accordance with an embodiment. Referring first to FIG. 3 and step 102 in FIG. 1, a substrate 202 is provided, wherein the substrate 202 comprises a first semiconductor material having a first lattice constant and hence is also referred to as first semiconductor material 202 in the present disclosure. In one embodiment, the substrate 202 comprises a crystalline silicon substrate (e.g., wafer). In alternative embodiments, the substrate 202 comprises a silicon-on-insulator (SOI) structure. The substrate 202 may comprise various doped regions depending on design requirements (e.g., p-type substrate or n-type substrate). In some embodiments, the doped regions may be doped with p-type or n-type dopants. For example, the doped regions may be doped with p-type dopants, such as boron or BF₂; n-type dopants, such as phosphorus or arsenic; and/or combinations thereof. The doped regions may be configured for an n-type FinFET, or alternatively configured for a p-type FinFET.

Still referring to FIG. 3, a second semiconductor material 204 (such as silicon germanium layer 204) epitaxially grown over the silicon substrate 202 (step 104 in FIG. 1), wherein the second semiconductor material 204 has a second lattice constant greater than the first lattice constant. For example, in an embodiment, the substrate 202 may be a silicon wafer and the second semiconductor material 204 is a silicon germanium layer. In this example, the germanium layer has about 25% to about 75% germanium, and may have a strained or fully relaxed surface. Additionally, the second semiconductor material 204 may be a uniform layer having a uniform concentration of, for example, germanium, or a gradient layer wherein the concentration of, for example, germanium varies.

In an embodiment, the second semiconductor material 204 (such as silicon germanium layer) is selectively grown by a chemical vapor deposition (CVD) process, such as a low-pressure CVD (LPCVD). In one embodiment, the LPCVD process is performed at a temperature of about 350° C. to about 800° C. and under a pressure of about 1 mTorr to about 760 Torr, using, for example, SiH₄, Si₂H₆, or the like as a silicon precursor and GeH₄, Ge₂H₆, or the like as a germanium precursor. In some embodiments, the silicon germanium layer 204 has a thickness ranging from about 10 nm to about 50 nm.

Still referring to FIG. 3, a third semiconductor material 206 (such as a germanium layer) is epitaxially grown over the second semiconductor material 204 (step 104 in FIG. 1), wherein the third semiconductor material 206 has a third lattice constant greater than the second lattice constant. As such, the second lattice constant is between the first lattice constant and the third lattice constant. In an embodiment, the third semiconductor material 206 comprises a germanium layer selectively grown by an LPCVD process. In an embodiment, the LPCVD process is performed at a temperature of about 200° C. to about 700° C. and under a pressure of about 1 mTorr to about 760 Torr, using GeH₄ or Ge₂H₆ as a precursor. In some embodiments, the third semiconductor material 206 has a thickness ranging from about 10 nm to about 50 nm. In an embodiment, a surface of the third semiconductor material 206 is fully relaxed.

For convenience, the second semiconductor material 204 is also referred to herein as the silicon germanium layer 204, and the third semiconductor material 206 is also referred to herein as the germanium layer 206. It should be noted, however, that other embodiments may utilize other materials, such as other group III-V materials, SiC, and the like.

FIGS. 4-5 illustrate forming a plurality of trenches (such as trenches 210 in FIG. 5) into the substrate 202, the silicon germanium layer 204, and the germanium layer 206 in accordance with an embodiment, similar to that discussed above with reference to step 106 in FIG. 1. Referring first to FIG. 4, there is shown a patterned mask 208 defining openings 208 a. In an embodiment, the patterned mask 208 is a photoresist layer that has been deposited, exposed, and developed. Other masking layers, such as oxide and/or nitride hard mask layers, may also be used.

The exposed germanium layer 206 is then etched to form a plurality of trenches 210. In some embodiments, the plurality of trenches 210 extends through the germanium layer 206, silicon germanium layer 204, and into the silicon substrate 202. In some embodiments, the trenches 210 may be strips (viewed from the top of the FinFET 200) parallel to each other, and closely spaced with respect to each other. In some embodiments, the trenches 210 may be continuous and surrounding the remaining germanium layer 206 and remaining silicon germanium layer 204. In some embodiments, the etching process may be performed using CF₄, HBr, CH₃F, SF₆, a mixture thereof, or the like as an etching gas, a carrier gas such as He or the like, and an passivation gas such as O₂ or the like. In an embodiment the process gas may be a combination of the etching gas, a carrier gas, and a passivation gas and may be used to etch the Ge, SiGe, and the Si material, although at different etch rates. In an embodiment, the trenches 210 may have a depth D1 of about 20 nm to about 120 nm.

In the depicted embodiments, the remaining germanium layer 206, remaining silicon germanium layer 204, and remaining silicon substrate 202 between trenches 210 are form a fin structure 220 (shown in FIG. 5). Further, the remaining germanium layer 206 is hereinafter referred to as an upper fin portion 220 u. The remaining silicon germanium layer 204 is hereinafter referred to as a middle fin portion 220 m. The protruding sections of the substrate 202 between trenches 210 are hereinafter referred to as a lower fin portion 220 l.

As such, the fin structure 220 comprises a lower fin portion 220 l comprising a first semiconductor material 202 having a first lattice constant; a middle fin portion 220 m comprising a second semiconductor material 204 having a second lattice constant greater than the first lattice constant; and an upper fin portion 220 u comprising a third semiconductor material 206 having a third lattice constant greater than the first lattice constant and the second lattice constant, wherein the middle fin portion 220 m is between the lower fin portion 220 l and upper fin portion 220 u. In the depicted embodiment, there are three fins extending from the substrate 202.

The patterned mask 208 is removed and a cleaning process is performed. In an embodiment, an SPM clean comprising a dilute mixture of H₂SO₄ and H₂O₂ may be used. Additionally, a cleaning process using, for example, diluted hydrofluoric (DHF) acid may be performed to remove a native oxide of the silicon substrate 202.

The process steps up to this point have provided the substrate 202 having the trenches 210 surrounding the fin structure 220. Conventionally, by introducing a dielectric material, such as shallow-trench-isolation (STI) oxide, in the trenches 210, each fin of the fin structure 220 is isolated from neighboring fins. However, the step of forming the dielectric material may create interface traps between the fin and dielectric material. The generated interface traps may provide a carrier transportation path between the fin and the dielectric material and cause high leakage current of the FinFET, thereby degrading the device performance.

Accordingly, the processing discussed below forms a passivation structure on exposed surfaces of the fin structure 220 to impede generation of the interface traps between the fin and STI oxide. Problems associated with high leakage current due to high interface traps may be reduced and/or avoided. Thus, embodiments disclosed herein may achieve the desired device performance characteristics, such as low leakage.

As depicted in FIG. 6, and discussed above with reference to step 108 in FIG. 1, a passivation structure is formed on exposed surfaces of the fin structure 220 to enhance device performance. In an embodiment, the passivation structure 230 is an oxynitride formed by an oxidation and nitridation process. As discussed above, the fin structure 220 may be formed of different materials, such as the silicon substrate 202, the silicon germanium layer 204 and the germanium layer 206. The oxidation and nitridation processes may react differently with these materials, forming, for example, a silicon oxynitride (SiON) layer on the silicon substrate 202, a silicon germanium oxynitride (SiGeON) on the silicon germanium layer 204, and a germanium oxynitride (GeON) on the germanium layer 206. The first passivation layer may have a thickness of about 0.5 nm to about 5 nm.

Accordingly, FIG. 6 illustrates a first passivation layer 230 comprising a lower passivation portion 230 l over the silicon substrate 202, a middle passivation portion 230 m over the silicon germanium layer 204, and an upper passivation portion 230 u over the germanium layer 206. Due to the different materials, the lower passivation portion 230 l over the silicon substrate 202 is a SiON layer, the middle passivation portion 230 m over the silicon germanium layer 204 is a SiGeON layer, and the upper passivation portion 230 u over the germanium layer 206 is a GeON layer.

As such, the first passivation layer 230 over the fin structure 220 comprises the lower passivation portion 230 l over the lower fin portion 220 l comprising an oxynitride of the first semiconductor material 202; the upper passivation portion 230 u over the upper fin portion 220 u comprises an oxynitride of the third semiconductor material 206; and the middle passivation portion 230 m between the lower passivation portion 230 l and upper passivation portion 230 u, wherein the middle passivation portion 230 m over the middle fin portion 220 m comprises an oxynitride of the second semiconductor material 204.

The first passivation layer 230 acts as a buffer layer between the fin 220 and a subsequently formed insulating layer (such as STI oxide 216 in FIG. 8) to impede generation of the interface traps. Problems associated with high leakage current due to high interface traps may be reduced and/or avoided, thereby achieving better performance characteristics, such as low leakage.

In the depicted embodiment, the step of forming the first passivation layer 230 over the fin structure 220 is performed by an oxidation process, followed by a nitridation process. In some embodiments, the oxidation process comprises a rapid thermal oxidation (RTO) process, high pressure oxidation (HPO), chemical oxidation process, in-situ stream generation (ISSG) process, or enhanced in-situ stream generation (EISSG) process. In some embodiments, the RTO process is performed at a temperature of about 400° C. to about 700° C., using O₂ and O₃ as reaction gases, for about 1 second to about 30 seconds. In other embodiments, an HPO is performed using a process gas of O₂, O₂+N₂, N₂, or the like at a pressure from about 1 atm to about 25 atm and a temperature from about 300° C. to about 700° C. for about 1 minute to about 180 minutes. Examples of a chemical oxidation process include wet SPM clean, wet O₃/H₂O, or the like. The O₃ may have a concentration of about 1 ppm to about 50 ppm.

In some embodiments, the nitridation process comprises rapid thermal nitridation (RTN) process, high pressure nitridation (HPN), or decoupled plasma nitridation (DPN) process. In some embodiments, the RTN process is performed at a temperature of about 400° C. to about 800° C., using NH₃ as reaction gas, for about 1 second to about 180 seconds. In some embodiments, the HPN process is performed using a process gas of NH₃ at a pressure from about 1 atm to about 25 atm and a temperature from about 300° C. to about 700° C. for about 1 minute to about 180 minutes. In some embodiments, the DPN process is performed under a power of about 300 Watts to about 2250 Watts, using a process gas of N₂, NH₃, N₂+Ar, N₂+He, NH₃+Ar, or the like as process gases.

In some embodiments, a post nitridation anneal (PNA) process is performed after the DPN process. In some embodiments, the PNA is performed at a temperature of about 400° C. to about 700° C., using N₂ as anneal gas, for about 1 second to about 180 seconds. The PNA process causes the GeO to react with the N to reach a stable state, as well as driving the N deeper to create a more uniform layer.

The ratio of y:x (N:O) in the oxynitride layers (e.g., SiO_(x)N_(y), SiGeO_(x)N_(y), and GeO_(x)N_(y)) may be controlled through process condition adjustment, such as plasma power or temperature, for a particular application. In some embodiments, a ratio of y:x is between about 0.25 to about 0.90.

In some embodiments, some elements in the second semiconductor material 204 (such as germanium in the silicon germanium layer 204) may diffuse into the first semiconductor material 202 (such as the silicon substrate 202) during the nitridation process. As such, the middle passivation portion 230 m may extend along a portion over the lower fin portion 220 l. In some embodiments, a first height H₁ of the middle passivation portion 230 m is equal to or greater than a second height H₂ of the middle fin portion 220 m as illustrated in FIG. 6. In some embodiments, a ratio of the first height H₁ to the second height H₂ is from about 1 to about 1.2.

FIG. 7 depicts the resulting structure after forming a dielectric material 212 in the trenches 210, such as discussed above with reference to step 110 of FIG. 1. The dielectric material 212 may include silicon oxide, and hence is also referred to as STI oxide 212 in the present disclosure. In some embodiments, other dielectric materials, such as silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), or a low-K dielectric material, may also be used. In some embodiments, the STI oxide 212 may be formed using a spin-on-dielectric (SOD) process, such as hydrogen silsesquioxane (HSQ) or methyl silsesquioxane (MSQ). In other embodiments, the STI oxide 212 may be formed using a high-density-plasma (HDP) CVD process, using silane (SiH₄) and oxygen (O₂) as reacting precursors. In other embodiments, the STI oxide 212 may be formed using a sub-atmospheric CVD (SACVD) process or high aspect-ratio process (HARP), wherein process gases may comprise tetraethylorthosilicate (TEOS) and ozone (O₃).

In an embodiment, the STI oxide 212 is formed to a thickness greater than a height of the fins 220 and subsequently recessed using a planarization process and an etch process. The planarization process, such as a CMP, reduces the STI oxide 212 to an upper surface of the first passivation layer 230. A subsequent etch process reduces the height of the STI oxide 212 to expose portions of the sidewalls of the fin 220, resulting in recesses 214.

In some embodiments, the etching step may be performed using a wet etching process, for example, by dipping the substrate 202 in dilute hydrofluoric acid (HF). In some embodiments, the etching step may be performed using a vapor etching process, for example, the vapor etching process may be performed using HF as etching gas.

In an embodiment, the STI oxide 212 is recessed such that an upper surface of the STI oxide 212 is at or below an interface between the upper fin portion 220 u and the middle fin portion 220 m. In an embodiment, a height H₃ of the exposed fin is about 10 nm to about 50 nm, and width W₃ is about 6 nm to about 20 nm.

Referring now to FIG. 8, a fin reshaping process is performed in accordance with an embodiment, and as discussed above with reference to step 112 of FIG. 1. The reshaping process results in multiple crystal facets being exposed along a surface of the fin 220. For example, in an embodiment an upper surface of the fin 220 may have a crystal orientation of (001) and a sidewall of the fin 220 may have a crystal orientation of (110). Between these crystal orientations, the fin surface may also exhibit crystal orientations of (113) and (111). By reshaping the fin, higher mobility may be obtained as compared to unshaped fins. In an embodiment in which the upper fin portion 220 u comprises germanium, the reshaping may be performed using a wet etch of hot ammonia at a temperature of 20° C. to about 100° C. Such an etch process removes the upper passivation portion 230 u and reshapes the upper fin portion 220 u. As a result of the reshaping process, exposed portions of the fin 220 exhibits slanted sidewalls.

FIG. 9 illustrates a second passivation process in accordance with an embodiment, and as discussed above with reference to step 112 of FIG. 1. The second passivation process results in a second passivation layer 910 formed on exposed surfaces of the reshaped fin, the upper fin portion 220 u in the illustrated embodiment. The second passivation process may use similar processes as the first passivation process discussed above with reference to FIG. 6. The second passivation layer 910 may have a thickness of about 0.5 nm to about 5 nm.

In some embodiments, the second passivation layer 910 comprises GeO_(x)N_(y), wherein the ratio of y:x (N:O) is about 0.25 to about 0.9. A ratio such as this has been found to allow for a Dit (interface trap density—a measure of dangling bond concentration per cm²) of about 1E10/cm2, whereas without the second passivation layer the Dit may be less than 1E12, such as about 1E11.

Furthermore, the y:x ratio of the second passivation layer along a top surface of the upper fin portion 220 u may be adjusted to be different from the y:x ratio of the second passivation layer along sidewalls of the upper fin portion 220 u. The y:x ratio of the second passivation layer oxynitride may be controlled through process condition adjustment, such as plasma power or temperature. In some embodiments, a first ratio of y:x of the second passivation layer 910 along an upper surface of the upper fin portion 220 u is equal to or greater than a second ratio of y:x of the second passivation layer 910 along sidewalls of the upper fin portion 220 u. In some embodiments, a ratio of the first ratio to the second ratio is from about 1 to about 1.3. In some embodiments, a higher y:x ratio may result in a lower etching rate or lower thermal effect.

Thereafter, additional processes may be performed. For example, FIG. 10 illustrates a gate structure 912 formed over portions of the fin 220. Portions of the upper fin portion 220 u comprise source/drain (S/D) regions along either side of the gate electrode 912 b, and a channel region extends between the S/D regions below the gate electrode 912. In some embodiments, the gate structure 912 comprises a gate dielectric 912 a and a gate electrode 912 b as shown in FIG. 10.

As illustrated in FIG. 10 the first passivation layer and/or the second passivation layer over the fin structure 220 to impede generation of the interface traps between the fin 220 and STI oxide 212, or another overlying dielectric (e.g., an interlayer dielectric), problems associated with high leakage current due to high interface traps may be reduced and/or avoided, thereby resulting in increased device performance characteristics, such as low leakage.

It is understood that the FinFET 200 may undergo further processes. For example, CMOS processes may be performed to form various features such as contacts/vias, interconnect metal layers, dielectric layers, passivation layers, etc.

FIGS. 11-18 illustrate various intermediate process steps of another embodiment. As discussed above, FIGS. 3-10 illustrate an embodiment in which the fins 220 comprise a lower fin portion 220 l, a middle fin portion 220 m, and a upper fin portion 220 u, wherein each has a different composition. As explained below FIGS. 11-18 illustrate an embodiment in which the fins will be formed of two different materials, rather than the three different materials as illustrated in FIGS. 3-10. Where appropriate, reference is made to the structures and processes described above, wherein like reference numerals refer to like elements unless otherwise noted.

Referring first to FIG. 11, there is shown the substrate 202 having the second semiconductor material 204 (also referred to as the silicon germanium layer 204) formed thereon. As discussed above the substrate 202 may be formed of silicon and the second semiconductor material 204 may be formed of silicon germanium, wherein similar processes as described above with reference to FIG. 3 may be used.

In this embodiment, the silicon germanium layer 204 may be epitaxially grown to a thickness of about 20 nm to about 50 nm. The silicon germanium layer 204 may exhibit a strained surface and have a concentration of germanium from about 25% to about 75%.

FIGS. 12 and 13 illustrate the patterning of the substrate 202 and the silicon germanium layer 204, thereby forming trenches 210 interposed between fins 220. In this embodiment as illustrated in FIG. 13, the fins 220 comprise a lower fin portion 220 l and a upper fin portion 220 u. In an embodiment, the lower fin portion 220 l is formed from a silicon substrate and may be patterned in a similar manner as the lower fin portion 220 l discussed above with reference to FIGS. 4 and 5, and the upper fin portion 220 u is formed from a silicon germanium material and may be patterned in a similar manner as the middle fin portion 220 m (formed also of silicon germanium) discussed above with reference to FIGS. 4 and 5. It is noted that for convenience, that FIGS. 13-18 refer to a upper fin portion 220 u, although the material of the upper fin portion 220 u may be different than the material of the upper fin portion 220 u referred to in FIGS. 5-10. It is also noted that other materials may be used. In an embodiment a depth D₁ of the trench is about 20 nm to about 120 nm.

FIG. 14 illustrates a first passivation process to form a first passivation layer 230 in accordance with an embodiment. Similar processes as those disclosed above with reference to FIG. 6 may be used. In an embodiment, the first passivation layer 230 comprises an oxynitride. For example, in an embodiment in which the lower fin portion 220 l comprises a silicon substrate, a lower passivation portion 230 l may be formed of silicon oxynitride and in an embodiment in which the upper fin portion 220 u comprises silicon germanium, an upper passivation portion 230 u may be formed of silicon germanium oxynitride.

FIG. 15 illustrates forming an STI oxide 212 in the trenches 210 (see FIG. 14), creating recesses 214, in accordance with an embodiment. Similar processes as those disclosed above with reference to FIG. 7 may be used. In an embodiment, a height H₃ of the fin 220 above an upper surface of the STI oxide 212 is about 10 nm to about 50 nm, and a width W₃ of 6 nm to about 20 nm.

FIG. 16 illustrates a fin reshaping process and FIG. 17 illustrates a second passivation process to form a second passivation layer 910 in accordance with an embodiment. Similar processes as those disclosed above with reference to FIGS. 8 and 9 may be used.

Thereafter, additional processes may be performed. For example, FIG. 18 illustrates a gate structure 912 formed over portions of the fin 220. Similar processes and structures may be used as discussed above with reference to FIG. 10.

FIGS. 19-26 illustrate various intermediate process steps of another embodiment. As discussed above, FIGS. 3-10 illustrate an embodiment in which the fins 220 comprise a lower fin portion 220 l, a middle fin portion 220 m, and a upper fin portion 220 u, wherein each has a different composition, and FIGS. 11-18 illustrate an embodiment in which the fins 220 comprise a lower fin power 220 l and a upper fin portion 220 u. As explained below FIGS. 19-26 illustrate an embodiment in which the fins will be formed of two different materials wherein the elemental concentrations of one element varies, rather than the three different materials as illustrated in FIGS. 3-10 and two different materials as illustrated in FIGS. 11-18. Where appropriate, reference is made to the structures and processes described above, wherein like reference numerals refer to like elements unless otherwise noted.

Referring first to FIG. 19, there is shown the substrate 202 having the second semiconductor material 204 (also referred to as the silicon germanium layer 204) formed thereon. As discussed above the substrate 202 may be formed of silicon and the second semiconductor material 204 may be formed of silicon germanium, wherein similar processes as described above with reference to FIG. 3 may be used.

In this embodiment, the silicon germanium layer 204 comprises a first silicon germanium layer (Si_(x1)Ge_(y1)) 204 a and a second silicon germanium layer (Si_(x2)Ge_(y2)) 204 b, wherein the relative concentrations of germanium differs between the first silicon germanium layer 204 a and the second silicon germanium layer 204 b. The first silicon germanium layer 204 a may act as a buffer layer to the second germanium layer 204 b to reduce defects and to control the strain in a surface of the second germanium layer 204 b. In an embodiment, y1 is less than y2, thereby creating a compressive strain in a surface of the second germanium layer 204 b. In an embodiment, y2 is less than y1, thereby creating a tensile strain in a surface of the second germanium layer 204 b.

In an embodiment, the first silicon germanium layer 204 a may be epitaxially grown to a thickness of about 20 nm to about 50 nm and the second silicon germanium layer 204 b may be epitaxially grown to a thickness of about 20 nm to about 50 nm.

FIGS. 20 and 21 illustrate the patterning of the substrate 202, the first silicon germanium layer 204 a and the second silicon germanium layer 204 b, thereby forming trenches 210 interposed between fins 220. In the illustrated embodiment, the fins 220 comprises a lower fin portion 220 l, a middle fin portion 220 m, and a upper fin portion 220 u, formed from the substrate 202, the first silicon germanium layer 204 a and the second silicon germanium layer 204 b, respectively. It is noted that for convenience, that FIGS. 21-26 refer to a middle fin portion 220 m and a upper fin portion 220 u, although the material of the middle fin portion 220 m and the upper fin portion 220 u of FIGS. 21-26 may be different than the material of the middle fin portion 220 m and the upper fin portion 220 u referred to in FIGS. 5-10. In an embodiment in which the substrate 202 is a silicon substrate, the substrate 202 may be etched as discussed above with reference to FIGS. 4 and 5. In an embodiment in which the first silicon germanium layer 204 a and the second silicon germanium layer 204 b are formed of silicon germanium, the first silicon germanium layer 204 a and the second silicon germanium layer 204 b may be etched in a similar manner as the silicon germanium layer discussed above with reference to FIGS. 4 and 5. In an embodiment a depth D1 of the trench is about 20 nm to about 120 nm.

FIG. 22 illustrates a first passivation process to form a first passivation layer 230 in accordance with an embodiment. Similar processes as those disclosed above with reference to FIG. 6 may be used. In this embodiment, the first passivation process results in a lower passivation portion 230 l, a middle passivation portion 230 m, and an upper passivation portion 220 u, although the middle passivation portion 230 m and the upper passivation portion 230 u of this embodiment may correspond to different materials than the middle passivation portion 230 m and the upper passivation portion 230 u of FIG. 6. In this embodiment, the concentration of Ge in the SiGeON layer may vary according to the concentration of Ge in the first silicon germanium layer 204 a and the second silicon germanium layer 204 b. For example, the upper passivation portion 220 u over the first silicon germanium layer 204 a may be expressed as Si_(x1)Ge_(y1)ON and the middle passivation portion 220 u over the second silicon germanium layer 204 b may be expressed as Si_(x2)Ge_(y2)ON.

FIG. 23 illustrates forming an STI oxide 212 in the trenches 210 (see FIG. 22), creating recesses 214, in accordance with an embodiment. Similar processes as those disclosed above with reference to FIG. 7 may be used. In an embodiment, a height H₃ of the fin 220 above an upper surface of the STI oxide is about 20 nm to about 50 nm.

FIG. 24 illustrates a fin reshaping process and FIG. 25 illustrates a second passivation process to form a second passivation layer 910 in accordance with an embodiment. Similar processes as those disclosed above with reference to FIGS. 8 and 9 may be used.

Thereafter, additional processes may be performed. For example, FIG. 26 illustrates a gate structure 912 formed over portions of the fin 220. Similar processes and structures may be used as discussed above with reference to FIG. 10.

The embodiments discussed above may be selected for a particular application. For example, an embodiment utilizing a Ge fin may be better suited for an N-FET, whereas SiGe may be better suited for a P-FET. Particular embodiments may be selected to achieve the desired strain and defect control. Furthermore, the percentage of Ge in SiGe may be adjusted to obtain the desired strain.

In an embodiment, a FinFET is provided. The FinFET comprises a substrate and a fin structure protruding from the substrate, the fin structure comprising one or more semiconductor layers, each of the semiconductor layers having a different lattice constant of a corresponding immediately underlying layer. An isolation region is adjacent opposing sidewalls of the fin structure, the fin structure having an upper portion extending above the isolation region, the upper portion having slanted sidewalls. A first passivation layer is interposed between the fin structure and the isolation region, and a second passivation layer is on the upper portion of the fin structure. A gate structure overlies the upper portion of the fin structure. The fin structure may comprise, for example, a silicon germanium layer on a silicon substrate and a germanium layer on the silicon germanium layer. In other embodiments, the fin structure may comprise a silicon germanium layer on a silicon substrate. In in yet other embodiments, the fin structure may comprise multiple silicon germanium layers having different germanium concentrations on a silicon substrate.

In yet other embodiments, a method of forming a FinFET is provided. The method includes providing a substrate and forming one or more fins extending from the substrate, each of the one or more fins having one or more semiconductor layers overlying the substrate, each of the one or more fins having a lattice constant different than a lattice constant of an underlying layer. A first passivation layer is formed over the one or more fins, and isolation regions are formed along opposing sidewalls of the one or more fins such that the one or more fins extending above an uppermost surface of the isolation regions. A reshaping process is performed on exposed portions of the one or more fins, and a second passivation layer is formed over the reshaped exposed portions of the one or more fins.

In yet still other embodiments, a FinFET is provided. The FinFET includes a substrate, a fin structure protruding from the substrate, the fin structure comprising one or more semiconductor layers, each of the semiconductor layers having a different lattice constant of an immediately underlying layer, and an isolation region adjacent opposing sidewalls of the fin structure, the fin structure having an upper portion extending above the isolation region, the upper portion having slanted sidewalls. The FinFET further includes a first passivation layer interposed between the fin structure and the isolation region and a second passivation layer on the upper portion of the fin structure. A gate structure overlies the upper portion of the fin structure.

In yet still other embodiments, a FinFET is provided. The FinFET includes a substrate having a fin structure, the fin structure comprising one or more semiconductor layers, each of the semiconductor layers having a different lattice constant of an immediately underlying layer, the fin structure having a lower portion and an upper portion, the upper portion having a lesser slope than the lower portion and an isolation region adjacent opposing sidewalls of the fin structure, an upper surface of the isolation region being level with a junction between the upper portion and the lower portion. The FinFET further includes a first passivation layer interposed between the fin structure and the isolation region and a second passivation layer on the upper portion of the fin structure. A gate structure overlies the upper portion of the fin structure.

In yet still other embodiments, a FinFET is provided. The FinFET includes a fin structure comprising one or more semiconductor layers, each overlying semiconductor layer of the one or more semiconductor layers having a different lattice constant of a corresponding immediately underlying semiconductor layer of the one or more semiconductor layers, the fin structure having a lower portion and an upper portion. The FinFET further includes a first passivation layer along sidewalls of the lower portion of the fin structure, an isolation region over the first passivation layer along opposing sidewalls of the fin structure, and a second passivation layer on sidewalls of the upper portion of the fin structure, an interface between the first passivation layer and the second passivation layer being aligned with an upper surface of the isolation region. A gate dielectric layer overlies the second passivation layer, and a gate electrode overlies the gate dielectric layer.

While the disclosure has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements. 

What is claimed is:
 1. A fin field effect transistor (FinFET) comprising: a substrate; a fin structure protruding from the substrate, the fin structure comprising one or more semiconductor layers, each of the one or more semiconductor layers having a different lattice constant than an immediately underlying layer; an isolation region on opposing sides of the fin structure, wherein the fin structure has a first sidewall profile extending from an upper surface of the fin structure to a bottom of the isolation region along a shortest path, the first sidewall profile having an upper portion and a lower portion, a slope of the upper portion being different than a slope of the lower portion, the upper portion of the first sidewall profile being a sidewall of a channel region; and a gate structure overlying the upper portion of the first sidewall profile and overlying the isolation region.
 2. The FinFET of claim 1, wherein lower portion contacts the upper portion at a point, wherein the point is level with an upper surface of the isolation region.
 3. The FinFET of claim 1, wherein the fin structure comprises a lower portion below the channel region, wherein the gate structure comprises a gate dielectric layer and a gate electrode, and further comprising: a first passivation layer interposed between the isolation region and the lower portion of the first sidewall profile; and a second passivation layer interposed between the gate structure and the upper portion of the first sidewall profile.
 4. The FinFET of claim 3, wherein the channel region comprises a germanium layer, the lower portion of the fin structure comprises a silicon germanium layer, the second passivation layer comprises GeON, and the first passivation layer comprises SiGeON.
 5. The FinFET of claim 3, wherein the channel region comprises an upper section of a silicon germanium layer, the lower portion of the fin structure comprises a lower section of the silicon germanium layer, the first passiviation layer comprises SiGeON, and the second passivation layer comprises SiGeON.
 6. The FinFET of claim 3, wherein the channel region comprises a first Si_(x1)Ge_(y1) layer, the lower portion of the fin structure comprises a second Si_(x2)Ge_(y2) layer, the first passivation layer comprises SiGeON, and the second passivation layer comprises SiGeON, wherein x1 is less than y1.
 7. The FinFET of claim 3, wherein the channel region comprises a first Si_(x1)Ge_(y1) layer, the lower portion of the fin structure comprises a second Si_(x2)Ge_(y2) layer, the first passivation layer comprises SiGeON, and the second passivation layer comprises SiGeON, wherein x1 is greater than y1.
 8. A fin field effect transistor (FinFET) comprising: a substrate having a fin structure, the fin structure having a first section, the first section of the fin structure comprising one or more semiconductor layers, each of the one or more semiconductor layers having a different lattice constant than an immediately underlying layer; a gate structure overlying an entirety of the first section of the fin structure in a plan view; isolation regions along opposing sides of the first section of the fin structure, wherein opposing lower sidewalls of the first section of the fin structure below an upper surface of the isolation regions are parallel, wherein opposing upper sidewalls of the first section of the fin structure above the upper surface of the isolation regions taper toward each other as the opposing upper sidewalls extend away from the upper surface of the isolation regions; a first passivation layer interposed between the first section of the fin structure and the isolation regions; and a second passivation layer interposed between the first section of the fin structure and the gate structure.
 9. The FinFET of claim 8, wherein the first passivation layer comprises a first oxynitride layer.
 10. The FinFET of claim 9, wherein the first passivation layer comprises a second oxynitride layer.
 11. The FinFET of claim 10, wherein the first oxynitride layer and the second oxynitride layer comprise a silicon germanium oxynitride layer.
 12. The FinFET of claim 10, wherein the first oxynitride layer comprises a silicon oxynitride layer and the second oxynitride layer comprises a silicon germanium oxynitride layer.
 13. The FinFET of claim 8, wherein the one or more semiconductor layers comprises a first semiconductor layer and a second semiconductor layer on the first semiconductor layer, wherein the first semiconductor layer comprises a first semiconductor material, wherein the second semiconductor layer comprises a second semiconductor material, wherein the first passivation layer comprises a first oxynitride of the first semiconductor material, wherein the second passivation layer comprises a second oxynitride of the second semiconductor material, wherein a first height of the first passivation layer is greater than a second height of the first semiconductor material.
 14. The FinFET of claim 13, wherein a ratio of the first height to the second height is from about 1 to about 1.2.
 15. A fin field effect transistor (FinFET) comprising: a substrate having a fin structure, the fin structure comprising one or more semiconductor layers, each semiconductor layer of the one or more semiconductor layers having a different lattice constant of an immediately underlying semiconductor layer of the one or more semiconductor layers, the fin structure having a first sidewall, the first sidewall intersecting a first plane orthogonal to a major surface of the substrate at a first interface; an isolation region adjacent a lower portion of the first interface, wherein the first plane intersects the isolation region; and a gate structure adjacent an upper portion of the first interface, wherein the first plane intersects the gate structure, wherein the lower portion of the first interface has a first slope, wherein the upper portion of the first interface has a second slope different than the first slope, wherein the lower portion of the first interface contacts the upper portion of the first interface at a first point.
 16. The FinFET of claim 15, wherein the gate structure comprises a gate dielectric and a gate electrode.
 17. The FinFET of claim 15 further comprising a first passivation layer interposed between the lower portion of the first interface and the isolation region, and further comprising a second passivation layer interposed between the upper portion of the first interface and the gate structure, wherein the first passivation layer comprises a different material than a material of the second passivation layer.
 18. The FinFET of claim 17, wherein a thickness of the first passivation layer and a thickness of the second passivation layer are greater than or equal to 0.5 nm and less than or equal to 5 nm.
 19. The FinFET of claim 15, wherein the first point is level with an upper surface of the isolation region.
 20. The FinFET of claim 15, wherein the one or more semiconductor layers comprise a first semiconductor layer and a second semiconductor layer, wherein an interface between the first semiconductor layer and the second semiconductor layer is level with an upper surface of the isolation region. 